Black box design of software and/or hardware systems has become common in application-specific integrated circuit (ASIC) design, field programmable gate array (FPGA) design, and other digital and/or mixed-signal systems. Black box design involves selecting predefined elements for inclusion in a design without the need to see or understand the workings of the selected element. The input ports and output ports of a block box cell are defined, and the outputs for given inputs are clearly documented. A user provides inputs to the block-box cell and receives outputs from the black box cell without needing to understand or edit the internal components of the black box cell. Black box cells may be defined by a user library or provided by software and/or hardware vendors.
Black box cells, however, present a problem in timing analysis, including clock domain crossing (CDC), false path, and multi-cycle path analysis. In modern chip design it is not uncommon for a design to use multiple clocks, possibly driven at different frequencies and/or asynchronous to each other. A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock. If the two clocks in this scenario have not been synchronized, then the input signal to the second flop may not be stable when it is sampled, a situation called metastability. A false path occurs when a section of logic is not exercised during normal operation. The false path may be an error, or may exist for some other reason, in which case it can be ignored during timing analysis. A multi-cycle path is a timing path that is designed to take more than one clock cycle for data to propagate along the path.
Electronic design automation (EDA) software tools are capable of analyzing a design for clock domain crossings, and alerting the user if a clock domain crossing has occurred between two clock domains that are not synchronized. Black box cells, however, do not provide information about their internal operation; therefore, timing analysis tools are unable to determine which outputs from the black box are driven by which input clocks. Timing analysis tools thus typically leave black box cells out of the analysis. Black box cells are not immune from clock domain crossing issues, and thus what is needed are systems and methods for including black box cells in timing analysis.